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to pidsa hq AN44067A-VF 1203030 receipt date: / / issuance date: / / panasonic global part number vendor issue number orderer (customer) part number "changes in the description of delivery specifications" and "chang es that affect performance, quality or environment" are imple mented according to advance consultation. orderer (customer) vendor confirmation of security control we confirm and certify that the products of these specifications sha ll not be supplied so as to be used for military purpose (de fined herein below). "military purpose" in this statem ent means the design, development, manufactu re, storage or use of any weapons, includi ng without limitation nuclear weapons, biologi cal weapons, chemical weapons and missiles. delivery specifications industrial devices company, panasonic corporation smart puniness distraction s423140-10#01 3.12 2012.
request for your special attention and precautions in using the technical information and semiconductors described in this book (1) if any of the products or technical information described i n this book is to be exported or provided to non-residents, the laws and regulations of the expo rting country, especially, those with regard to security export control, must be observed. (2)the technical information described in this book is intended only to show the main characteristics and application circuit examples of the products. no license is granted in and to any intellectual property right or other right owned by panasonic corporation or any other company. therefore, no responsibility is assumed by our company as to the infringement upon any such right owned by any other company which may arise as a result of the use of technical inf ormation de-scribed in this book. (3)the products described in this book are intended to be used for general applications (such as office equipment, communications equipment, measuring instrumen ts and household appliances), or for specific applications as expressly stated in this book. consult our sales staff in advance for information on the follo wing applications: ?special applications (such as for airplanes, aerospace, automo tive equipment, traffic signaling equipment, combustion equipment, life support systems and safet y devices) in which exceptional quality and reliability are required, or if the failure or malfunction of the products may directly jeopardize life or harm the human body. it is to be understood that our company shall not be held respo nsible for any damage incurred as a result of or in connection with your using the products describ ed in this book for any special application, unless our company agrees to your using the produc ts in this book for any special application. (4)when designing your equipment, comply with the range of abso lute maximum rating and the guaranteed operating conditions (operating power supply voltage and operat ing environment etc.). especially, please be careful not to exceed the range of absolute maximum r ating on the transient state, such as power-on, power-off and mode-switching. other-wise, we will not be liable for any defect which may arise later in your equipment. even when the products are used within the guaranteed values, t ake into the consideration of incidence of break down and failure mode, possible to occur to semiconduc tor products. measures on the systems such as redundant design, arresting the spread of fire or preve nting glitch are recommended in order to prevent physical injury, fire, social damages, for example, by using the products. (5)comply with the instructions for use in order to prevent bre akdown and characteristics change due to external factors (esd, eos, thermal stress and mechanical st ress) at the time of handling, mounting or at customer's process. when using products for which damp-pr oof packing is required, satisfy the conditions, such as shelf life and the elapsed time since first opening the packages. (6)this book may be not reprinted or reproduced whether wholly or partially, without the prior written permission of our company. reprint from warning label standards sc3-11-00007 this delivery specifications may include old company names such as ?matsushita electronics corporation? o r ?semiconductor company, matsushita electric industrial co., ltd .??semiconductor company, panasonic corporation ? please interpret these old company names as industrial devices company, panasonic corporation? as of january 1, 2012.
established revised product standards regulations no.: total pages page 1 45 an44067a part no. package code no. hsop034-p-0300a part no. package code no. semiconductor company, matsushita electric industrial co., ltd. established by applied by checked by prepared by semiconductor company matsushita electric industrial co., ltd. 214406700108020 m.hiramatsu h.nobekawa t.nagano 2008-02-20 ic3f5158
2 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700208020 2008-02-20 contents ? overview ????????????????????.????????????????????? 3 ? features ???????????????????.?????????????????????? 3 ? applications ???????????????????.????????????????????? 3 ? package ???????????????????.??????????????????????. 3 ? type ?????????????????????.??????????????????????. 3 ? application circuit example ????????????????????????????????? 4 ? block diagram ??????????????????.????????????????????? 5 ? pin descriptions ????????????????.?????????????????????? 6 ? absolute maximum ratings ????????????.????????????????????? 7 ? operating supply voltage range ????????.????????? ?????????????? 7 ? allowable current and voltage range ????????????? ???????????????? 8 ? electrical characteristics ?????.????????????????????????????? 9 ? electrical characteristics (reference values for design) ?????.????????????????. 11 ? test circuit diagram ???????????.????????????????????????? 12 ? electrical characteristics test procedures ????.???????????????????????. 14 ? technical data ????????????????.??????????????????????? 22 1. i/o block circuit diagrams and pin function descriptions ????????????? ???????. 22 2. control mode ?????.???? ??????????.????.?? ????????????? 28 3. each phase current value ???????????.??????????.?????.?????? 29 4. each phase current (timing chart) ??????????.??????????.?????.??? 31 5. timing chart at change of dir??????????.??????????.?????.?????? 35 6. home position function?.??????????????.????.??????????????? 36 ? usage notes ????????????????. ????????????? ??????????. 38 1. special attention and precaution in using ????????? ???????????? ??????. 38 2. notes of power lsi ????????????????????????????????????. 39 3. notes ????????????????.???????????????????????.??. 40
3 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700308020 2008-02-20 an44067a driver ic for stepping motor ? overview an44067a is s two channel h-bridge driv er ic. bipolar stepping motor can be controlled by a single driver ic. 2 phase excitation, half- step, 1-2 phase excitation, w1-2 phase excitation and 2w1-2 phase excitation can be selected. ? features y built-in decoder for micro steps (2 phase excitation, hal f-step, 1-2 phase excitation, w1-2 phase excitation and 2w1-2 phase excitation) stepping motor can be driven by only external clock signal. y pmw can be driven by built-in cr (3-value can be selected during pwm off period.) selection during pwm off period enables the best pwm drive. y mix decay compatible (4-value for fast decay ratio can be selected.) mix decay control can improve accura cy of motor current wave form. y built -in low voltage detection if supply voltage lowers less than the range of operating supply voltage, low voltage detection operates an d all phases of motor drive output are turned off. y built-in thermal protection if chip junction temperature rises and reaches setup temperature, all phases of motor drive output are turned off. y 1 power supply with built-in 5 v power supply (accuracy 5%) motor can be driven by only 1 power s upply because of built- in 5 v power supply. y built-in standby function operation of standby function can lower current consumption of ic. y built-in home position function home position function can detect the position of a motor. ? applications y ic for stepping motor drives ? package y 34 pin plastic small outline package with heat sink (sop type) ? type y bi-cdmos ic
4 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700408020 2008-02-20 ? application circuit example notes) y this application circuit is shown as an example but does not guarantee the design for mass production set. 0.01 f 0.01 f 0.1 f 0.1 f 15 vpump enable 19 6 bout2 8 bout1 decay2 20 decay1 21 12 aout1 10 aout2 s5vout 24 tjmon 3 pwmsw 33 test stby uvlo uvlo gate circuit vref 23 r s q 7 rcsb gate circuit 11 rcsa blank osc tsd bg 17 vm1 1vm2 vm pwmsw 47 f pha 28 dir 32 st2 30 st3 29 r qs st1 31 s5vout amp stby 22 dacb test 25 27 gnd 4 gnd protection of gnd aout1 aout2 vm charge pump bc1 13 bc2 14 protection of gnd bout1 bout2 vm 1/10 1/10 100 k only test = high-level input daca micro step decoder
5 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700508020 2008-02-20 ? block diagram note) this block diagram is for explaining functions. the part of the block diagram may be omitted, or it may be simplified. 15 vpump enable 19 6 bout2 8 bout1 decay2 20 decay1 21 12 aout1 10 aout2 s5vout 24 tjmon 3 pwmsw 33 test stby uvlo uvlo gate circuit vref 23 r s q 7 rcsb gate circuit 11 rcsa blank osc tsd bg 17 vm1 1vm2 vm pwmsw pha 28 dir 32 st2 30 st3 29 r qs st1 31 s5vout amp stby 22 dac2 test 25 27 gnd 4 gnd protection of gnd aout1 aout2 vm charge pump bc1 13 bc2 14 protection of gnd bout1 bout2 vm 1/10 1/10 dac1 micro step decoder
6 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700608020 2008-02-20 ? pin descriptions ? ? n.c. 34 step select 1 input st1 31 step select 2 input st2 30 step select 3 input st3 29 internal reference voltage (output 5 v) output s5vout 24 torque reference voltage input input vref 23 standby input stby 22 mix decay setup 1 input decay1 21 mix decay setup 2 input decay2 20 enable / disable ctl input enable 19 ? ? n.c. 18 motor power supply 1 power supply vm1 17 pwm off period selection input input pwmsw 33 rotation direction input dir 32 clock input input pha 28 signal ground ground gnd 27 die pad ground ground gnd 26 test mode input test 25 ? ? n.c. 16 charge pump circuit output output vpump 15 charge pump capacitor connection 2 output bc2 14 charge pump capacitor connection 1 output bc1 13 phase a motor drive output 1 output aout1 12 phase a current detection input / output rcsa 11 phase a motor drive output 2 output aout2 10 die pad ground ground gnd 9 phase b motor drive output 1 output bout1 8 phase b current detection input / output rcsb 7 phase b motor drive output 2 output bout2 6 ? ? n.c. 5 ground ground gnd 4 vbe monitor / test output / home position output output tjmon 3 ? ? n.c. 2 motor power supply 2 power supply vm2 1 description type pin name pin no.
7 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700708020 2008-02-20 ? absolute maximum ratings *5, *6 a 2.5 i out motor drive current (pin 6, 8, 10, 12) 6 *4 v 37 v out output pin voltage (pin 6, 8, 10, 12) 5 *2 w 0.466 p d power dissipation 2 notes unit rating symbol parameter a no. *5, *6 a 2.5 i f flywheel diode current (pin 6, 8, 10, 12) 7 *3 c ?55 to +150 t stg storage temperature 4 *3 c ?20 to +70 t opr operating ambient temperature 3 *1 v 37 v m supply voltage (pin 1, 17) 1 notes) *1 : the values under the condition not exceeding the above absolute maximum ratings and the power dissipation. *2 : the power dissipation shown is the value at t a = 70 c for the independent (unmounted) ic package without a heat sink. when using this ic , refer to the p d -t a diagram of the package standard and design the heat radiation with sufficie nt margin so that the allowable value might not be exceeded based on the conditi ons of power supply voltage, load, and ambient temperature. *3 : except for the power dissipation, operating ambient temp erature, and storage temperature, all ratings are for t a = 25 c. *4 : this is output voltage rating and do not a pply input voltage from outside to these pins. set not to exceed allowable range at any time. *5 : do not apply external currents to any pin specially mentione d. for circuit currents, (+) denotes current flowing into the i c and (?) denotes current flowing out of the ic. *6 : rating when cooling fin on the back side of the ic is c onnected to the gnd pattern of the glass epoxy 4-layer board. (gnd area : 2nd-layer or 3rd-layer : more than 1 500 mm 2 ) in case of no cooling fin on the back side of the ic, rating current is 1.5 a on the glass epoxy 2-layer board. note) absolute maximum ratings are limit values which are not dest ructed, and are not the values to which operation is guarantee d. ? operating supply voltage range supply voltage range * notes unit range symbol parameter v 10.0 to 34.0 v m notes) * : the values under the condition not exceeding the above absolute maximum ratings and the power dissipation.
8 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700808020 2008-02-20 ? v 2.5 rcsb 7 ? v 2.5 rcsa 11 *1 v (v m ?1) to43 bc2 14 *1 v (v m ?2)to43 vpump 15 ? v ?0.3 to 6 enable 19 ? v ?0.3 to 6 decay2 20 ? v ?0.3 to 6 decay1 21 ? v ?0.3 to 6 stby 22 ? v ?0.3 to 6 vref 23 ? v ?0.3 to 6 test 25 ? v ?0.3 to 6 pha 28 ? v ?0.3 to 6 st3 29 ? v ?0.3 to 6 st2 30 ? v ?0.3 to 6 st1 31 ? v ?0.3 to 6 dir 32 ? v ?0.3 to 6 pwmsw 33 notes unit rating pin name pin no. *2 ma 1 tjmon 3 ? ma ?7 to 0 s5vout 24 notes unit rating pin name pin no. ? allowable current and voltage range notes) y voltage values, unless otherwise specified, are with respect to gnd. y do not apply external currents or voltages to any pin not specifically mentioned. y for the circuit currents, "+" denotes current flowing into the ic, and " ? " denotes current flowing out of the ic. y voltages and currents below show the limit value of nondestructive range which must not be exceeded in a moment. ? ) *1 : these are pins not applied voltage from outside. set so that the rating must not be exceeded transiently. *2 : in case of test = high-level input, tjmon voltage is only low-level. (detail : refer to electrical characteristics no. 52 described in page 10).
9 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406700908020 2008-02-20 ? a 150 83 40 pwmsw = 5 v 1 i pwmswh high-level pwmsw input current 23 ? v 0.6 ? 0 ? 1 v pwmswl low-level pwmsw input voltage 22 ? ma 10 5.5 ? enable = high, stby = high 1 i m supply current (active) 5 ? a ?18 ?36 ?70 pwmsw = 0 v 1 i pwmswl low-level pwmsw input current 24 ? v 1.7 ? 1.3 ? 1 v pwmswm middle-level pwmsw input voltage 21 ? v 5.5 ? 2.3 ? 1 v pwmswh high-level pwmsw input voltage 20 ? a 2 ? ?2 enable = 0 v 1 i enablel low-level enable input current 19 ? a 100 50 25 enable = 5 v 1 i enableh high-level enable input current 18 ? v 0.6 ? 0 ? 1 v enablel low-level enable input voltage 17 ? v 5.5 ? 2.1 ? 1 v enableh high-level enable input voltage 16 ? khz 100 ? ? ? 1 f pha highest-level pha input frequency 15 ? a 2 ? ?2 pha = 0 v 1 i phal low-level pha input current 14 ? v 1.7 1.5 1.3 ? 1 v pwmswo pwmsw voltage at open 25 ? a 100 50 25 pha = 5 v 1 i phah high-level pha input current 13 ? v 0.6 ? 0 ? 1 v phal low-level pha input voltage 12 ? v 5.5 ? 2.1 ? 1 v phah high-level pha input voltage 11 ? a 2 ? ?2 stby = 0 v 1 i stbyl low-level stby input current 10 ? a 100 50 25 stby = 5 v 1 i stbyh high-level stby input current 9 ? v 0.6 ? 0 ? 1 v stbyl low-level stby input voltage 8 ? v 5.5 ? 2.1 ? 1 v stbyh high-level stby input voltage 7 i/o block v m = 37 v, v rcs = 0 v i = 1.2 a ? v 1.5 1.0 0.5 i = 1.2 a 2 v di flywheel diode forward voltage 3 ? a 20 10 ? 2 i leak output leakage current 4 ? a 50 25 ? stby = low 1 i mstby supply current (stby) 6 output drivers ? v ? v m ?0.42 v m ?0.75 i = ?1.2 a 2 v oh high-level output saturation voltage 1 ? v 0.825 0.54 ? 2 v ol low-level output saturation voltage 2 limits typ unit max test circuits notes min conditions symbol parameter b no. ? electrical characteristics at v m = 24.0 v note) t a = 25 c 2 c unless otherwise specified.
10 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701008020 2008-02-20 reference voltage block ? mv 525 500 475 v ref = 5 v 1 vt cmp comp threshold 49 ? s 1.0 0.7 0.4 v ref = 0 v 1 t b pulse blanking time 48 ? s 11.3 8.1 4.9 pwmsw = high 1 t off3 pwm off time 3 47 ? s 21.3 15.2 9.1 pwmsw = middle 1 t off2 pwm off time 2 46 ? v 5.25 5.0 4.75 i s5vout = 0 ma 1 v s5vout reference voltage 50 ? s 39.2 28 16.8 pwmsw = low 1 t off1 pwm off time 1 45 ? a 2 ? ?2 v ref = 0 v 1 i refl input bias current 2 44 ? a 5 ? ?15 v ref = 5 v 1 i refh input bias current 1 43 ? v 0.3 0.1 ? pull up tjmon pin to 5 v with 100 k . 1 v tjl at test high-level input tjmon output low-level voltage 52 home position block ? 10 ? ? i s5vout = ?7 ma 1 z s5vout output impedance 51 torque control block ? a 2 ? ?2 test = 0 v 1 i testl low-level test input current 42 ? a 100 50 25 test = 5 v 1 i testh high-level test input current 41 ? v 0.6 ? 0 ? 1 v testl low-level test input voltage 40 ? v 2.7 ? 2.3 ? 1 v testm middle-level test input voltage 39 ? v 5.5 ? 4.0 ? 1 v testh high-level test input voltage 38 ? a 5 ? ? v tjmon = 5 v 1 i tj(leak) at test high-level input tjmon output leakage current 53 ? a 2 ? ?2 st1 = st2 = st3 = 0 v 1 i stl low-level st input current 37 ? a 100 50 25 st1 = st2 = st3 = 5 v 1 i sth high-level st input current 36 ? v 0.6 ? 0 ? 1 v stl low-level st input voltage 35 ? v 5.5 ? 2.1 ? 1 v sth high-level st input voltage 34 ? a 2 ? ?2 dir = 0 v 1 i dirl low-level dir input current 33 ? a 100 50 25 dir = 5 v 1 i dirh high-level dir input current 32 ? v 0.6 ? 0 ? 1 v dirl low-level dir input voltage 31 decay1 = decay2 = 0 v ? ? a 100 50 25 decay1 = decay2 = 5 v 1 i decayh high-level decay input current 28 ? a 2 ? ?2 1 i decayl low-level decay input current 29 ? v 5.5 ? 2.1 ? 1 v dirh high-level dir input voltage 30 ? v 5.5 ? 2.1 ? 1 v decayh high-level decay input voltage 26 ? v 0.6 ? 0 1 v decayl low-level decay input voltage 27 limits typ unit max test circuits notes min conditions symbol parameter b no. ? electrical characteristics (continued) at v m = 24.0 v note) t a = 25 c 2 c unless otherwise specified.
11 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701108020 2008-02-20 ? electrical characteristics (reference values for design) at v m = 24 v notes) t a = 25 c 2 c unless otherwise specified. the characteristics listed below are reference values derived fr om the design of the ic and are not guaranteed by inspection. if a problem does occur related to these characteris tics, we will respond in good faith to user concerns. low voltage protection ? v ? 8.7 ? ? ? v uvlo2 protection releasing voltage 60 ? ? output voltage fall ? s ? 0.8 ? ? ? t d dead time 56 thermal protection ? c ? 150 ? ? ? tsd on thermal protection operating temperature 57 ? c ? 40 ? ? tsd thermal protection hysteresis width 58 output drivers ? v/ s ? 220 ? output voltage rise ? vt r output slew rate 1 54 ? v/ s ? 200 ? ? vt f output slew rate 2 55 ? v ? 7.9 ? ? v uvlo1 protection operating voltage 59 reference values typ unit max test circuits notes min conditions symbol parameter b no.
12 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701208020 2008-02-20 1. test circuit 1 ? test circuit diagram 31 st1 25 test 34 n.c. rcsb 7 bout2 6 n.c. 2 vm2 1 gnd 4 gnd 9 rcsa 11 26 gnd 22 stby 28 pha 23 vref bout1 8 30 st2 27 gnd 18 n.c. 32 dir vpump 15 bc1 13 bc2 14 vm1 17 24 s5vout 33 pwmsw aout2 10 aout1 12 n.c. 16 19 enable tjmon 3 n.c. 5 20 decay2 21 decay1 29 st3 i pha v pha a v enable i enable v i vm v m = 24 v a 0.01 f i stby v stby a a i pwmsw v pwmsw a v s5out i s5vout v v ref i ref a v st2 i st2 a a i st1 v st1 a i dir v dir 0.01 f s5 v rcsb v st3 i st3 a i decay2 v decay2 a i decay1 v decay1 a i test v test a 5 v s6 100 k s7 1 k s8 2 1 3 5 v a i tjmon s9 12 v 2 1 75 3 s1 s2 s3 s4 v aout1 v 12 v 2 1 75 3 v aout2 v 12 v 2 1 75 3 v bout1 v 12 v 2 1 75 3 v bout2 v 10k 10k 2 1 3 5.6 v rcsa 1 k 2 1 3 5.6
13 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701308020 2008-02-20 2. test circuit 2 ? test circuit diagram 31 st1 25 test 34 n.c. rcsb 7 bout2 6 n.c. 2 vm2 1 gnd 4 gnd 9 rcsa 11 26 gnd 22 stby 28 pha 23 vref bout1 8 30 st2 27 gnd 18 n.c. 32 dir vpump 15 bc1 13 bc2 14 vm1 17 24 s5vout 33 pwmsw aout2 10 aout1 12 n.c. 16 19 enable tjmon 3 n.c. 5 20 decay2 21 decay1 29 st3 v pha v m 5 v v saout2 i aout2 s3 i saout2 a v aout2 v v saout1 i aout1 s4 a v aout1 v v sbout2 i bout2 s1 i sbout2 2 1 a s2 v bout2 v 0.6 v 0.6 v 0.6 v 0.6 v 0.6 v 0.6 v 0.6 v 2.1 v 0.6 v 2 1 2 1 i saout1 v enable 0.01 f 0.01 f s5 v sbout1 i bout1 i sbout1 2 1 a v bout1 v s6
14 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701408020 2008-02-20 1. test circuit 1 off off off on off off off off off off off off off off off s9 hi-z 0 v 0 v 0 v 0 v 0 v hi-z 0 v 2.1 v 0 v 0 v 1 1 on 1 33 25 hi-z 5 v 0.6 v, 2.3 v, 2.7 v, 4.0 v 0.6 v 0.6 v 0 v 0.6 v 0.6 v 5 v v decay1 = 0.6 v v decay2 = 2.1 v 2.1 v 1 1 or 2 on 2 3, 6, 8, 10, 12, 25 38, 39, 40 1 2 1 1 1 1 1 1 1 1 1 1 1 s7, s8 1 1 1 1 1 1 1 1 1 1 1 1 1 s6 hi-z 5 v 0.6 v 0.6 v 0.6 v 0 v 5 v 0.6 v 2.1 v 0.6 v 0.6 v ? 2.1 v 200 khz pulse on 2 6, 8, 10, 12, 28 11, 12,15 hi-z 5 v 0 v 0.6 v 0.6 v 0.475 v, 0.525 v 0 v 0.6 v 2.1 v 0 v 5 v off 3 6, 7, 8, 10, 11, 12 49 hi-z 5 v 0 v 0.6 v 0.6 v 0 v 0 v 2.1 v 2.1 v 0 v 0 v on 2 6, 8, 10, 12, 19 16 hi-z 5 v 0.6 v 5.5 v 5.5 v 0 v 5.5 v 2.1 v 2.1 v 5.5 v 0 v on 1 1, 17, 22 5, 7 hi-z 5 v 0.6 v 0.6 v 0.6 v 0 v 0.6 v 2.1 v 0.6 v 0.6 v 0.6 v on 1 1, 17, 22 6, 8 0 v 0 v 0 v 0 v 0 v 5 v 5.5 v 5.5 v v pwmsw hi-z 5 v 0 v 0.6 v 0.6 v 0 v 0.6 v 2.1 v 0 v 0 v on 2 6, 8, 10, 12, 19 17 hi-z 0 v 0 v 0 v 0 v 0 v 0 v 2.1 v 0 v 0 v on 1 23 44 hi-z 5 v 0 v 0 v 0 v 0 v 0 v 2.1 v 0 v 0 v on 1 23 43 hi-z 5 v 0 v 0 v 0 v 0 v 0 v 0 v 0 v 0 v on 3 22 10 i s5vout v ref v test v st1 v st2 v st3 v dir v rcsa v rcsb v enable v stby v decay1 v decay2 v pha s5 s1 to s4 3 3 1 1 on on on on hi-z hi-z ?7 ma hi-z measuring pin c no. 5 v 5 v 5 v 5 v 0.6 v 5.5 v 5.5 v 0 v 0.6 v 2.1 v 5.5 v 0 v 24 50 0.6 v 5.5 v 5.5 v 0 v 0.6 v 2.1 v 5.5 v 0 v 24 51 5 v 5 v 5 v 0 v 5 v 5 v 5 v 5 v 19 to 22, 25, 28 to 33 9, 13, 18, 23, 28, 32, 36, 41 0 v 0 v 0 v 0 v 0 v 5 v 0 v 0 v 19 to 21, 25, 28 to 33 14, 19, 24, 29, 33, 37, 42 ? electrical characteristics test procedures
15 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701508020 2008-02-20 16) enable high-level input voltage v enableh 17) enable low-level input voltage v enablel v enable 0.6 v v aout1 /v bout1 2.1 v v enableh v enablel 12 v spec 24 v spec 0 v region (a) region (b) 49) comp threshold vt cmp v rcsa / v rcsb v aout2 /v bout2 12 v 24 v 0 v region (a) region (b) check the conditions by measuring v aout2 and v bout2 voltage with the input voltage set to 0.475 v and 0.525 v respectively. region (a) : always output low-level region (b) : output low-level with minimum duty 51) output impedance z s5vout v s5out i s5vout 0 ma ?7 ma v s5vout v a z s5vout = 7ma v s5vout ?v a v enable 0.6 v v aout2 /v bout2 2.1 v v enableh v enablel 12 v spec 24 v spec 0 v region (a) region (b) 0.475 v 0.525 v spec spec ? electrical characteristics test procedures (continued) 1. test circuit 1 (continued)
16 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701608020 2008-02-20 11) pha high-level input voltage v phah 12) pha low-level input voltage v phal 15) pha highest input frequency f pha v pha v aout1 24 v 12 v 0 v 2.1 v 0.6 v 24 v 12 v 0 v v bout1 v aout2 24 v 12 v 0 v 24 v 12 v 0 v v bout2 200 khz f aout1 f aout2 f bout1 f bout2 check pha high, low and highes t input voltage in case of input of the pulse of 200 khz (low-level voltage = 0.6 v, high-level voltage = 2.1 v) to pha and the frequency of v aout1 ,v aout2 , v bout1 , v bout2 = 50 khz as the timing chart in the right figure. 38) test high-level input voltage v testh 39) test middle-level input voltage v testm 40) test low-level voltage v testl check that output status follows as the below chart when low-level (0.6 v), middle-level (2.3 v, 2.7 v) and high-level ( 4.0 v) are applied to test pin. 2 1 1 s6 4.0 v 2.3 v / 2.7 v 0.6 v test pin voltage conditions tjmon pin = home position output (for detail, refer to page 36, 37) test high-level input voltage output transistor all off v aout1 , v aout2 , v bout1 , v bout2 = 12 v tjmon pin = vbe monitor status test low-level input voltage test middle-level input voltage parameter chart output status at input vo ltage of low, middle, high-level ? electrical characteristics test procedures (continued) 1. test circuit 1 (continued)
17 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701708020 2008-02-20 off off off s9 hi-z 0 v 0.6 v 0.6 v 0.6 v ? refer to the next page 0.6 v 2.1 v refer to the next page pulse input 3 1 on 2 6, 8, 10, 12, 20, 21, 28, 33 20, 21, 22, 26, 27, 45, 46, 47, 48 hi-z 5 v 4 v v st1 =v st2 = 0.6 v v st3 = 2.1 v 0.6 v 0 v 0.6 v 0.6 v 2.1 v v decay1 = 2.1 v v decay2 = 2.1 v pulse input 1 2 or 3 on 1 3 52, 53 1 s7, s8 hi-z 5 v 0.6 v refer to below chart refer to below chart 0 v 0.6 v 0.6 v 2.1 v v decay1 = 2.1 v v decay2 = 2.1 v pulse input 1 on 2 6, 8, 10, 12, 28 to 32 30, 31, 34, 35 s6 v pwmsw i s5vout v re f v test v st1 v st2 v st3 v dir v rcsa v rcsb v enable v stb y v decay1 v decay2 v pha s5 s1 to s4 measuring pin c no. 30) dir high -level input voltage v dirh 31) dir low-level input voltage v dirl 34) st high-level input voltage v sth 35) st low-level input voltage v stl check the dir low/high input voltage and st low/high input vo ltage by setting the voltages of dir, st1, st2, st3 to voltages following to the above chart and checking the operation of each excitation mode (page 31 to 34). half-step drive (8-step sequence) / reverse 0.6 v 2.1 v 0.6 v 2.1 v w1-2 phase drive (16-step sequence) / reverse 0.6 v 2.1 v 2.1 v 2.1 v 1-2-phase excitation (8-step sequence) / reverse 0.6 v 0.6 v 2.1 v 2.1 v 2.1 v 2.1 v 0.6 v 0.6 v 0.6 v 0.6 v 0.6 v dir 0.6 v 0.6 v 0.6 v 2.1 v 2.1 v 0.6 v 0.6 v st1 2.1 v 0.6 v 2.1 v 2.1 v 0.6 v 2.1 v 0.6 v st2 2.1 v 0.6 v 2.1 v 0.6 v 0.6 v 0.6 v 0.6 v st3 2w1-2-phase driver (32-step sequence) / reverse 2 phase excitation drive (4-step sequence) / reverse 2w1-2-phase drive (32-step sequence) / forward w1-2-phase drive (16-stepsequence) / forward 1-2 phase excitation drive (8-step sequence) / forward half-step drive (8-step sequence) / forward 2 phase excitation drive (4-step sequence) / forward exciting mode ? electrical characteristics test procedures (continued) 1. test circuit 1 (continued)
18 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701808020 2008-02-20 20) pwmsw high-level input voltage v pwmswh 21) pwmsw middle-level input voltage v pwmswm 22) pwmsw low-level input voltage v pwmswl 26) decay high-level input voltage v decayh 27) decay low-level input voltage v decayl 45) pwm off time 1 t off1 46) pwm off time 2 t off2 47) pwm off time 3 t off3 48) pulse blanking time t b each value is obtained by the timing chart of v aout1 (v bout1 ) and v aout2 (v bout2 ) at vref = 0 v the timing chart of v aout1 (v bout1 )/v aout2 (v bout2 ) is shown as below. ? for 20) to 22), 45) to 47), check t off1 /t off2 /t off3 on the input conditions of pwms w pin in the below chart. ? for 26), 27), check t decay / t off on the conditions of decay1/decay2 in th e below chart in case of pwmsw high, middle, low-level input voltage. ? for 48), check low-level interval of v aout1 (v bout1 ) : t b in the below chart. t off2 = 15.2 s 1.3 v t off2 = 15.2 s 1.7 v v pwmswh / v pwmswm / v pwmswl t off3 = 8.1 s t off1 = 28 s 0.6 v pwmsw 2.3 v status voltage conditions input pin t b t[ s] v aout1 / (v bout1 ) v aout2 / (v bout2 ) t b 24 v 24 v 12 v 12 v 0 v 0 v t off1 / t off2 / t off3 t decay t[ s] t decay 100% mode 50% mode 25% mode 0% mode (slow decay) decay control (t decay / t off ) 2.1 v 0.6 v 0.6 v 2.1 v 2.1 v decay2 0.6 v 0.6 v 2.1 v decay1 chart t off to pwmsw input voltage chart decay control to decay1/2 input voltage ? electrical characteristics test procedures (continued) 1. test circuit 1 (continued)
19 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406701908020 2008-02-20 52) tjmon pin output low-level volt age at test pin high-level input v tjl 53) tjmon pin output leakage curr ent at test pin high-level input i tj(leak) check when tjmon pin in home position output timing chart is low and high-level. ? tjmon pin output low-level voltage at test pin high-level input v tjl check tjmon pin voltage by connection pull-up resister 100 k (to 5 v) to tjmon pin. ? tjmon pin output leakage current at test high-level input itj(leak) check the leakage current after applying 5 v to tjmon pin. 1 2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 10 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 pha 2w1-2 phase excitation tjmon iaout1 ibout1 home position output timing chart (dir = low-level) +100% ?100% 0% ? electrical characteristics test procedures (continued) 1. test circuit 1 (continued)
20 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702008020 2008-02-20 1) output saturation voltage high-level v oh 2) output saturation voltage low-level v ol off off off off off off off off s6 0.6 v 24 v on 2 i sbout2 = +1.2 a bout2/ v bout2 (h) 0.6 v 24 v on 2 i sbout1 = +1.2 a bout1/ v bout1 (g) 0.6 v 24 v on 2 i saout2 = +1.2 a aout2/ v aout2 (f) 0.6 v 24 v on 2 i saout1 = +1.2 a aout1/ v aout1 (e) on on on on s5 24 v 24 v 24 v 24 v v m 2 2 2 2 s1 to s4 i sbout2 = ?1.2 a i sbout1 = ?1.2 a i saout2 = ?1.2 a i saout1 = ?1.2 a applying conditions bout2/ v bout2 bout1/ v bout1 aout2/ v aout2 aout1/ v aout1 applying pin/ measuring voltage 0.6 v (a) 0.6 v 0.6 v 0.6 v v enable (b) (c) (d) v pha aout1 24 v 12 v 0 v 5 v 0 v 24 v 12 v 0 v bout1 aout2 24 v 12 v 0 v 24 v 12 v 0 v bout2 (a) (b) (c) (e) (f) (h) (d) (g) check output saturation voltage high and low-level on the below conditions ? electrical characteristics test procedures (continued) 2. test circuit 2
21 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702108020 2008-02-20 4) output leakage current i leak 5 v 37 v off on 1 v saout1 = v saout2 = v sbout1 = v sbout2 = 0 v aout1, aout2, bout1, bout2 / i aout1 , i aout2 , i bout1 , i bout2 (e), (f), (g), (h) on on on on s6 off off off off s5 1 1 1 1 s1 to s4 37 v 37 v 37 v 37 v v m v sbout2 = 37 v v sbout1 = 37 v v saout2 = 37 v v saout1 = 37 v applying conditions bout2 / i bout2 bout1 / i bout1 aout2 / i aout2 aout1 / i aout1 applying pin/ measuring current 0 v (a) 0 v 0 v 0 v v enable (b) (c) (d) 3) flywheel diode forward voltage v di on on on on s6 on on on on s5 0 v 0 v 0 v 0 v v m 2 2 2 2 s1 to s4 i sbout2 = 1.2 a i sbout1 = 1.2 a i saout2 = 1.2 a i saout1 = 1.2 a applying conditions bout2 / v bout2 bout1 / v bout1 aout2 / v aout2 aout1 / v aout1 applying pin/ measuring voltage 2.1 v 2.1 v 2.1 v 2.1 v v enable v pha 37 v 0 v 5 v 0 v 37 v 0 v 37 v 0 v 37 v 0 v (a) (c) (d) aout1 bout1 aout2 bout2 check flywheel diode forward voltage v di on the above conditions check output leakage current i leak *1 of each output pin on the above conditions note) *1 i leak : electrical characteristics no.4 shows absolute values. v enable 5 v 0 v (b) (e) (f) (g) (h) ? electrical characteristics test procedures (continued) 2. test circuit 2 (continued)
22 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702208020 2008-02-20 pin 6 : phase b motor drive output 2 7 : phase b current detection 8 : phase b motor drive output 1 10 : phase a motor drive output 2 11 : phase a current detection 12 : phase a motor drive output 1 ? ? 6 7 8 10 11 12 pin 3 : vbe monitor / test output / home position output ? ? 3 impedance description internal circuit waveform and voltage pin no. 3 800 pin3 tjmon pin 6 bout2 8 bout1 10 aout2 12 aout1 pin 7 rcsb 11 rcsa 4k 100k 15 100k 3k 500 167 793 ? technical data 1. i/o block circuit diagrams and pin function descriptions note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed.
23 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702308020 2008-02-20 pin 14 : charge pump capacitor connection 2 15 : charge pump circuit output ? ? 14 15 pin 13 : charge pump capacitor connection 1 ? ? 13 impedance description internal circuit waveform and voltage pin no. 15 14 300k 125 pin15 vpump pin14 bc2 13 150 125 pin13 bc1 ? technical data (continued) 1. i/o block circuit diagrams and pin function descriptions (continued) note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed.
24 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702408020 2008-02-20 pin 22 : standby 100 k ? 22 pin 19 : enable/disable ctl 20 : mix decay setup 2 21 : mix decay setup 1 28 : clock input 29 : step select 3 30 : step select 2 31 : step select 1 32 : rotation direction 100 k ? 19 20 21 28 29 30 31 32 impedance description internal circuit waveform and voltage pin no. pin19 enable 20 decay2 21 decay1 28 pha 29 st3 30 st2 31 st1 32 dir 4k 100k pin22 stby 68k 32k 22 ? technical data (continued) 1. i/o block circuit diagrams and pin function descriptions (continued) note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed.
25 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702508020 2008-02-20 pin 24 : internal reference voltage (output 5 v) ? ? 24 pin 23 : torque reference voltage input ? ? 23 impedance description internal circuit waveform and voltage pin no. pin23 vref 4k 4k 23 24 pin24 s5vout 50k 48k 100 1k ? technical data (continued) 1. i/o block circuit diagrams and pin function descriptions (continued) note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed.
26 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702608020 2008-02-20 pin 33 : pwm off period selection input ? ? 33 pin 25 : test mode 100 k ? 25 impedance description internal circuit waveform and voltage pin no. 60k 4k 140k 33 pin33 pwmsw 100k 4k 25 pin25 test ? technical data (continued) 1. i/o block circuit diagrams and pin function descriptions (continued) note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed.
27 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702708020 2008-02-20 ? ? ? ? impedance description internal circuit waveform and voltage pin no. s5vout (pin 24) vm(pin1, pin 17) diode zener diode ground ? technical data (continued) 1. i/o block circuit diagrams and pin function descriptions (continued) note) the characteristics listed below are reference values derived from the design of the ic and are not guaranteed.
28 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702808020 2008-02-20 off on high high low ? enable high low stby on on off off output transistor control /charge pump circuit 1) truth table (step select) ? high high low low ? st1 ? high low high low ? st2 output off ? ? high half-step drive (8-step sequence) low high low high high high high dir low low low low enable w1-2 phase drive (16-step sequence) low 2w1-2 phase drive (32-step sequence) high 1-2 phase excitation drive (8-step sequence) low low st3 2 phase excitation drive (4-step sequence) output excitation mode (phase b 90 advance to phase a) ? high high low low ? st1 ? high low high low ? st2 output off ? ? high half-step drive (8-step sequence) low low low low low low low dir low low low low enable w1-2 phase excitation drive (16-step sequence) low 2w1-2 phase excitation drive (32-step sequence) high 1-2 phase excitation drive (8-step sequence) low low st3 2 phase excitation drive (4-step sequence) output excitation mode (phase b 90 delay to phase a) 2) truth table (control/charge pump circuit) 8.1 s high 15.2 s 28.0 s pwm off period low middle pwmsw 4) truth table (decay selection) note) for each pwm off period, fast decay is applied according to the above table. 50% low high high high low decay2 slow decay low 25% low high decay1 100% decay control 3) truth table (pwm off period selection) home position output high test output (output transistor off) vbe monitor tjmon low middle test 5) truth table (test mode) ? technical data (continued) 2. control mode
29 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406702908020 2008-02-20 ?83.2 ?55.6 29 ?70.7 ?70.7 28 14 7 ?55.6 ?83.2 27 0 ?100 24 12 6 19.5 ?98.1 23 38.3 ?92.4 22 11 55.6 ?83.2 21 70.7 ?70.7 20 10 5 ?100 0 32 16 8 ?98.1 ?19.5 31 ?92.4 ?38.3 30 15 ?38.3 ?92.4 26 13 ?19.5 ?98.1 25 83.2 ?55.6 19 92.4 ?38.3 18 9 98.1 ?19.5 17 100 0 16 8 4 98.1 19.5 15 92.4 38.3 14 7 83.2 55.6 13 70.7 70.7 12 6 3 55.6 83.2 11 38.3 92.4 10 5 19.5 98.1 9 0 100 8 4 2 ?19.5 98.1 7 ?38.3 92.4 6 3 ?55.6 83.2 5 ?70.7 70.7 4 2 1 ?83.2 55.6 3 ?92.4 38.3 2 1 ?98.1 19.5 1 phase b current (%) phase a current (%) 2w1-2 phase (32 step) w1-2 phase (16 step) 1-2 phase (8 step) ? technical data (continued) 3. each phase current value 1) 1-2 phase, w1-2 phase, 2w1-2 phase dir = low note) the definition of phase a and b current 100% : (vref 0.1) / current detection resistance
30 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703008020 2008-02-20 phase b current (%) phase a current (%) 2w1-2 phase (32 step) w1-2 phase (16 step) 1-2 phase (8 step) ?83.2 55.6 29 ?70.7 70.7 28 14 7 ?55.6 83.2 27 0 100 24 12 6 19.5 98.1 23 38.3 92.4 22 11 55.6 83.2 21 70.7 70.7 20 10 5 ?100 0 32 16 8 ?98.1 19.5 31 ?92.4 38.3 30 15 ?38.3 92.4 26 13 ?19.5 98.1 25 83.2 55.6 19 92.4 38.3 18 9 98.1 19.5 17 100 0 16 8 4 98.1 ?19.5 15 92.4 ?38.3 14 7 83.2 ?55.6 13 70.7 ?70.7 12 6 3 55.6 ?83.2 11 38.3 ?92.4 10 5 19.5 ?98.1 9 0 ?100 8 4 2 ?19.5 ?98.1 7 ?38.3 ?92.4 6 3 ?55.6 ?83.2 5 ?70.7 ?70.7 4 2 1 ?83.2 ?55.6 3 ?92.4 ?38.3 2 1 ?98.1 ?19.5 1 ? technical data (continued) 3. each phase current value (continued) 1) 1-2 phase, w1-2 phase, 2w1-2 phase dir = high note) the definition of phase a and b current 100% : (vref 0.1) / current detection resistance
31 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703108020 2008-02-20 ? technical data (continued) 4. each phase current (timing chart) 1) 2 phase excitation drive (4-step sequence) (st1 = low, st2 = low, st3 = low) 2) half-step drive (8-step sequence) (st1 = low, st2 = high, st3 = low) fwd (dir = low) rev (dir = high) 123412341 iaout1 ibout1 clk 123412341 iaout1 ibout1 clk 123456781 iaout1 ibout1 clk 123456781 iaout1 ibout1 clk fwd (dir = low) rev (dir = high) +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0%
32 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703208020 2008-02-20 123456781 3) 1-2 phase excitation (8-step sequence) (st1 = high, st2 = low, st3 = low) iaout1 ibout1 clk fwd (dir = low) 123456781 iaout1 ibout1 clk rev (dir = high) +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% ? technical data (continued) 4. each phase current (timing chart) (continued)
33 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703308020 2008-02-20 4) w1-2 phase excitation (16-step sequence) (st1 = high, st2 = high, st3 = low) 123456789 11 12 13 14 15 16 1 10 iaout1 ibout1 clk fwd (dir = low) 123456789 11 12 13 14 15 16 1 10 iaout1 ibout1 clk rev (dir = high) +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% ? technical data (continued) 4. each phase current (timing chart) (continued)
34 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703408020 2008-02-20 5) 2w1-2 phase excitation (32-step sequence) (st3 = high) 1 2 3 4 5 6 7 8 9 11121314151617 10 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 iaout1 ibout1 clk fwd (dir = low) +100% ?100% 0% +100% ?100% 0% rev (dir = high) 123456789 11121314151617 10 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 iaout1 ibout1 clk +100% ?100% 0% +100% ?100% 0% ? technical data (continued) 4. each phase current (timing chart) (continued)
35 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703508020 2008-02-20 ? technical data (continued) 5. timing chart at change of dir (ex.1) timing chart at 1-2 phase excitation (dir low high) pha a-ch. motor current b-ch. motor current dir at change of dir, the state before the cha nge is held and the operation is continued. state 5 6 7 6 7 6 5 (ex.2) timing chart at 1-2 phase excitation (dir high low) pha a-ch. motor current b-ch. motor current dir state 3 4 5 4 3 2 1 at change of dir, the state before the cha nge is held and the operation is continued.
36 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703608020 2008-02-20 this lsi has built-in home position function to reduce the displacem ent of motor current state at change of excitation mode whi le a motor is driving. home position function , following as the below chart, outputs low-level voltage to tjmon pin at the timing when the displacement of motor current state is minimum at change of excitation mode in case of test = high-level input. at other timing, home position functi on outputs high-level voltage (in case th e pull-up resister (recommendation : 100 k to 5 v) is connected because tjmon pin is ma de with open drain) at tjmon pin. ?100% ?100% 2 phase excitation ?100% 0% 1-2 phase excitation ?100% 0% half-step ?100% ?100% phase b current 0% 0% phase a current 2w1-2 phase excitation w1-2 phase excitation table output current of each excitation mo de at home position = low (dir = low) 123456789 11121314151617 10 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 pha 2w1-2 phase tjmon iaout1 ibout1 w1-2 phase iaout1 ibout1 1-2 phase iaout1 ibout1 2 phase iaout1 ibout1 half-step iaout1 ibout1 1) home position output timing chart (dir = low) +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% ? technical data (continued) 6. home position function
37 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703708020 2008-02-20 ?100% ?100% 2 phase excitation ?100% 0% 1-2 phase excitation ?100% 0% half-step ?100% ?100% phase b current 0% 0% phase a current 2w1-2 phase excitation w1-2 phase excitation table output current of each excitation mo de at home position = low (dir = high) 1 2 3 4 5 6 7 8 9 11121314151617 10 18 19 20 21 22 23 24 25 27 28 29 30 31 32 1 26 pha 2w1-2 phase tjmon iaout1 ibout1 w1-2 phase iaout1 ibout1 1-2 phase iaout1 ibout1 2 phase iaout1 ibout1 half-step iaout1 ibout1 2) home position output timing chart (dir = high) +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% +100% ?100% 0% ? technical data (continued) 6. home position function (continued)
38 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703808020 2008-02-20 1. special attention and precaution in using 1. this ic is intended to be used for ge neral electronic equipment [stepping motor]. consult our sales staff in advance for in formation on the foll owing applications: x special applications in which ex ceptional quality and reli ability are required, or if the fail ure or malfunction of this ic may directly jeopardize life or harm the human body. x any applications other than the standard applications intended. (1) space appliance (such as artificial satellite, and rocket) (2) traffic control equipment (such as fo r automobile, airplane, train, and ship) (3) medical equipment for life support (4) submarine transponder (5) control equipment for power plant (6) disaster prevention and security device (7) weapon (8) others : applications of which reliability equivalent to (1) to (7) is required 2. pay attention to the direction of lsi. when mounting it in the wrong direction onto the pcb (printed-circuit-board), it might smoke or ignite. 3. pay attention in the pcb (printed-circuit-board) pattern layout in order to prevent damage due to short circuit between pins. in addition, refer to the pin description for the pin configuration. 4. perform a visual inspection on the pcb be fore applying power, otherwise damage might happen due to problems such as a solder- bridge between the pins of the semiconductor device. also, perfo rm a full technical verification on the assembly quality, becau se the same damage possibly can happen due to conductive substanc es, such as solder ball, that adhere to the lsi during transportation. 5. take notice in the use of this product that it might break or occasionally smoke when an abnormal state occurs such as output pin- v cc short (power supply fault), output pin-gnd short (ground fault), or output-to-output-pin short (load short) . especially, for the pins below, take notic e power supply fault, ground fault, load short and short between the pin below and current detection pin. (1) aout1(pin 12), aout2(pin 10), bout1(pin 8), bout2(pin 6) (2) bc1(pin 13), bc2(pin 14), vpump(pin 15) (3) vm1(pin 17), vm2(pin 1), s5vout(pin 24) (4) rcsa(pin 11), rcsb(pin 7) and, safety measures such as an installation of fuses are recommended because the extent of the above-mentioned damage and smoke emission will depend on the current capability of the power supply. 6. when using the lsi for new models, verify the safe ty including the long-term reliability for each product. 7. when the application system is designed by using this lsi, be sure to confirm notes in this book. be sure to read the notes to descriptions and the usage notes in the book. 8. connect the metallic plate (fin) on the back side of the ic with the gnd potential. the thermal resistan ce and the electrical characteristics are guaranteed only when the metallic plate (fin) is connected with the gnd potential. 9. confirm characteristics fully when using the lsi. secure adequate margin after considering variation of external part and this ic including not only static characteristics but transient characteristics. especia lly, pay attention that abnormal cu rrent or voltage must not be applied to external parts bec ause the pins (pin 6, 8, 10, 12, 13, 14, 15) output high current or voltage. ? usage notes
39 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406703908020 2008-02-20 ? usage notes (continued) 2. notes of power lsi. 1. design the heat radiation with sufficient margin so that po wer dissipation must not be exceeded base on the conditions of pow er supply voltage, load and ambient temperature. (it is recommended to design to set connectiv e parts to 70% to 80% of maximum rating) 2. the protection circuit is for maintainin g safety against abnormal operation. ther efore, the protection circuit should not wo rk during normal operation. especially for the thermal protection circuit, if the area of safe operation or the absolute maximum rating is momentarily exceeded due to output pin to vm short (p ower supply fault), or output pin to gnd short (ground fault), the lsi might be damaged before the thermal pr otection circuit could operate. 3. unless specified in the product specifications, make sure that negative voltage or excessive vo ltage are not applied to the p ins because the device might be damaged, which could happen due to negative voltage or excessive voltage generated during the on and off timing when the inductive load of a motor coil or actuator coils of optical pick-up is being driven. 4. the product which has specified aso (area of safe operation) shoul d be operated in aso. 5. verify the risks which might be cause d by malfunctions of external parts. 6. set capacitance value between vpump and gnd so that vpump (pin 15) must not exceed 43 v transiently at the time of motor standby to motor start. 7. this ic employs a pwm drive method that switches the high-current output of the output transistor. therefore, the ic is apt to generate noise that may caus e the ic to malfunction or have fatal damage. to prevent these problems, the power supply must be stable enough. therefore, the capacitance between the s5vout and gnd pins must be a minimum of 0.1 f and the one between the vm and gnd pins must be a minimum of 47 f and as close as possible to the ic so that pwm noise will not cause the ic to malfunction or have fatal damage.
40 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406704008020 2008-02-20 3. notes 1) pulse blanking time this ic has pulse blanking time (0.7 s/typ.value)to prevent erroroneous current detection caused by noise. therefore, the motor current value will not be less than curre nt determined by pulse blanking time. pay attention at the time of minimum current control. the relation between pulse blanking time and min imum current value is shown as chart 1. in addition, increase-decrease of motor cu rrent value is determined by l value, wire wound resi stance, induced voltage and pwm on duty inside a motor. t b t pwm at normal operation in case of setting less than minimum current value setup current value setup current value minimum current value t pwm : pwm off period t b : pulse blanking time (refer to electrical characteristics no.48) chart 1. rcs current waveform 2) vref voltage when vref voltage is set to low-level, erroroneous detection of current might be caused by noise because threshold of motor current detection comparator becomes low (= vref/10 motor current ratio [%] (refer to page 29, 30). use this ic after confirming no misdetection with setup ref voltage. 3) notes on interface absolute maximum of pin 19 to pin 23 and pin 28 to pin 33 is ?0. 3 v to 6 v. when the setup current for a motor is large and lead line of gnd is long, gnd pin potential might rise. take notice that interface pi n potential is negative to difference in potential between gnd pin reference and interf ace pin in spite of inputting 0 v to the interface pin. at that time, pay attent ion allowable voltage range must not be exceeded. 4) notes on test mode when inputting voltage of above 0.6 v and below 4.0 v to test (pin 25), this lsi might become test mode. when disturbance noise etc. makes this lsi test mode, motor out put pin might be hi-z. therefore, use this lsi on condition that test pin is shorted to gnd or s5 vout at normal motor operation. ? usage notes (continued)
41 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406704108020 2008-02-20 3. notes (continued) 5) notes on standby mode release / low voltage protection release this lsi has all phases off period of about 140 s (typ) owing to release of standby a nd low voltage protection (refer to the below figure). this is why restart from standby and low voltage protection is performed after booster voltage rises sufficiently because boost er operation stops at standby and low voltage protection. when the booster voltage does not rise sufficiently during all phases off period du e to that capacitance voltage between vpump and gnd becomes large etc., the ic might overheat. in this cas e, release standby and lo w voltage protection at enable = high-level, and restart at enable = low- level after the booster vo ltage rises sufficiently. moreover, take notice that state of moto r current becomes default position at stan dby and low voltage protection operation following as 3. notes no.8. motor output standby standby all phases off start (at enable = low) all phases off (at enable = high) stby about 140 s(typ) low high all phases off motor output all phases off restart (at enable = low) all phases off (at enable = high) vm about 140 s(typ) low high all phases off (low voltage protection) at standby release at low voltage protection release standby release ground fault detection ground fault detection about 5.5 s(typ) about 5.5 s(typ) 6) ground fault protection function this ic has built-in ground fault protection function to de tect ground fault of motor output pin at board mounting. as the above figure, ground fault detection function will operate after release of low voltage protection and standby, and chec k ground fault of motor output pins. if ground fault is detected, this function makes motor output a ll phases off and motor operation stop. if ground fault is not detected, this function makes motor start. however, take notice that ic might be destroyed before ground fault protection funct ion operates in case that aso ( area of safe operation ) of device or maximum rating are exceeded in a moment. in addition, this function might not detect ground fault when starting vm at stby = hi gh-level. it is reco mmended that vm is started at stby = low-level. in case of release of ground fault detection, restart ic afte r inputting low voltage to stby pin or making vm voltage off. 7) notes on release of thermal protection the release of thermal protection operation will restart after all phases off of about 140 s and ground fault detection operation as 3. notes no.5, 6. moreover, take notice that the state of motor current will b ecome default position after release of thermal protection operatio nas 3. notes no.8 ? usage notes (continued)
42 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406704208020 2008-02-20 default electrical angle excitation mode 0 1-2 phase excitation (8 step) 0 w1-2 phase excitation (16 step) 0 2w1-2 phase excitation (32 step) 0 half-step (8 step) ?45 2 phase excitation (4 step) aout1 current bout1 current default 0 default of half/ 1-2/w1-2/2w1-2 phases excitation default ?45 default of 2 phase excitation dir = low dir = high dir = low dir = high table default position of each excitation mode 3. notes (continued) 8) default of motor current state default of motor current follows as the below figure after rele ase of low voltage protection, standby and thermal protection on each excitation mode. a b cd pha dir 9) pha input signal and dir input signal the set/hold time of pha and dir input si gnals, pha input minimum pul se width (high/low) are shown as the below figure. input signals after securing set/hold time. 5 s or more pha input minimum pulse width (high) a 5 s or more pha input minimum pulse width (low) b dir hold time dir set time contents time period 2 s or more d 2 s or more c ? usage notes (continued)
43 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406704308020 2008-02-20 pha a-ch. motor current ex.) 1-2 phase excitation enable a-ch. motor current enable pha 7 8 1 2 1 2 3 4 5 6 3 4 5 6 7 8 in spite of stop at state[6] , because pha is input at enable = high, the motor will restart after enable = low at state [3]. 1 2 3 4 5 6 6 7 8 1 2 3. notes (continued) 10) pha input at enable = high as the below figure (ex. 1-2 phase exci tation), when inputting pha at the time of motor stop and enable = high (all phases are off motor current = 0 a), the setup value of motor current will proceed at pha input. therefore, in case of restart at enable = low, take notice that the position of restart is wh ere the current state just before motor stop gains pha input. low low low low high high in spite of stop at state [6] , because pha is not input at enable = high, the motor will restart after enable = low at state [6] just before stop. motor stop motor stop ? usage notes (continued)
44 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406704408020 2008-02-20 motor connecter gnd gnd rcsa/rcsb ic current limit detection resister point 1 point 2 point 3 (a) 3. notes (continued) 11) notes on rcs line take consideration in the below figure and the points and design pcb pattern. (1) point 1 design so that the wiring to the current detection pin (rcsa/rcsb pin) of this ic is thick and short to lower impedance. this is why current can not be detected correctly owing to wiri ng impedance and current might not be supplied to a motor sufficiently. (2) point 2 design so that the wiring between curre nt detection resister and c onnecter gnd (the below figure point 2) is thick and short to lower impedance. as the same as point 1, sufficien t current might not be supplied due to wiring impedance. in addition, if there is a common impedance on the side of gnd of rasa and rcsb, peak det ection might be erroroneous detection. therefore, install the wiring on the side of gnd of rcsa and rcsb independently. (3) point 3 connect gnd pin of this ic to the connecter on pcb indepe ndently. separate the wiri ng removed current detection resister of large current lin e (point 2) from gnd wiring and make these wirings one-point shorted at the connecter as the below figure. that can ma ke fluctuation of gnd minimum. 12) a high current flows into the ic. therefore, the common impeda nce of pcb can not be ignored. take the following points into consideration and design the pcb pattern for a motor. because the wiring connecting to vm1 (pin 17) and vm2 (pin 18)of this ic is high-current, it is easy to generate noise at time of switching by wiring l. that might cause malfunction and destruction ( figure 2 ). as figure 3, the escape way of the noise is secured by connecting a capacitor to the connector close to the vm pin of the ic. this makes it possible to suppress the fluctuation of di rect vm pin voltage of the ic. make the setting as shown in figure 3 as much as possible. figure 2. no recommended pattern vm gnd l c ic rcs vm gnd figure 3. recommended pattern vm gnd l c ic rcs vm gnd low spike amplitude due to capacitance between the vm pin and gnd pin ? usage notes (continued)
45 45 an44067a product standards established revised total pages page semiconductor company, matsushita electric industrial co., ltd. 214406704508020 2008-02-20 temp[ c] vbe[v] vbe / temp = ?1.86 [mv / c] 150 0 tjmon pin temperature characteristics 3. notes (continued) 13) ic junction temperature in case of measuring chip temperature of this ic, measure the voltage of tjmon pin (pin 3) and estimate the chip temperature from the data below. however, because this data is technical reference data, conduct a sufficient reliability test of the ic and evaluate the product with the ic incorporated. 14) speed of supply and cut of power when supplying to vm pin (pin 1, 17) , set th e rise speed of vm voltage to less than 0.1 v/ s and fall speed to less than 0.1 v/ s. if the speed of rise and fall of power supply is too ra pid, that might cause malfunction and destruction of the ic. in this case, conduct a sufficient reliability test and also check a sufficient evaluation for a product. supply voltage vm time less than 0.1 v/ s, rise less than 0.1 v/ s, fall ? usage notes (continued)
total pages page established semiconductor company, panasonic corporation package code regulations no. revised semiconductor company panasonic corporation package standards established by applied by checked by prepared by hsop034-p-0300a -- sc3s0829 61 m.itoh m.okajima h.yoshida h.shidooka established: 2004-03-18 revised : 2009-06-26
total pages page semiconductor company, panasonic corporation revised established package standards 62 -- unit:mm lead finish method : pd plating lead material : cu alloy body material : epoxy resin 1. outline drawing package code : hsop034-p-0300a established: 2004-03-18 revised : 2009-06-26
total pages page semiconductor company, panasonic corporation revised established package standards 63 -- 2. package structure (technic al report : reference value) package code : hsop034-p-0300a 1 2 3 4 method material method material method material 23 1 6 457 si transfer molding epoxy resin wirebond outer lead surface au cu alloy pd plating leadframe material inner lead surface chip material 5 6 7 resin adhesive method mass 250 mg pd plating adhesive material thermo-compression bonding molding chip mount established: 2004-03-18 revised : 2009-06-26
total pages page semiconductor company, panasonic corporation revised established package standards 64 -- 3. mark layout package code : hsop034-p-0300a product name brand mark date code 1-pin direction established: 2004-03-18 revised : 2009-06-26
total pages page semiconductor company, panasonic corporation revised established package standards 65 -- 4. power dissipation (technical report) package code : hsop034-p-0300a 0.000 0.200 0.400 0.600 0.800 1.000 1.200 1.400 1.600 0 25 50 75 100 125 150 ambient temperature ( o c ) power dissipation( ) without pwb rth(j-a) = 171.6 /w 1.453 0.728 mount on pwb glass-epoxy:50x50x0.8t(mm) rth(j-a) = 86.0 /w heat dissipation fin (daipaddo) the state where it does not mount established: 2004-03-18 revised : 2009-06-26
total pages page semiconductor company, panasonic corporation revised established package standards 66 -- 5. power dissipation (su pplementary explanation) package semiconductor element rth(j-c) rth(c-a) rth(j-a) ta tc tj pwb [ definition of each temperature and thermal resistance ] ta ambient air temperature t the temperature of the air is defined at the position where the convection, radiation, etc. don?t affect the temperature value, and it?s separated from the heating elements. tc it?s the temperature near the center of a packa ge surface. the package surface is defined at the opposite side if the pwb. tj semiconductor element surface tem perature (junction temperature.) rth(j-c) the thermal resistance ( difference of temperature of per 1 watts) between a semiconductor element junction part and the package surface rth(c-a) the thermal resistance (difference of temperature of per 1 watts) between the package surface and the ambient air rth(j-a) the thermal resistance (difference of temperature of per 1 watts) between a semiconductor element junction part and the ambient air [ supplementary information of pwb to be used for measurement ] the supplement of pwb information for power dissipation data (technical report are shown below. fr-4 4-layer 4-layer fr-4 1-layer glass-epoxy resin material total layer indication [notes about power dissipation thermal resistance ] power dissipation values thermal resistance depend on the conditions of the surroundings, such as specification of pwb and a mounting condition , and a ambient temperat ure. (power dissipation (thermal resistance) is not a fixed value.) the power dissipation value technical report is the experiment result in specific conditions (evaluation environment of semi standard conformity) ,and keep in mind that power dissipation values (thermal resistance) depend on circumference conditions and also change. [ experiment environment ] power dissipation technical report is a result in the experiment environment of semi standard conformity. ambient air temperature ( ta) is 25 degrees c [definition formula] rth(j-c) = tj-tc p rth(c-a) = tc-ta p rth(j-a) = tj-ta p ( ? /w) ( ? /w) ( ? /w) tj={rth(j-c)+rth(c-a)} p+ta =rth(j-a) p+ta p:power(w) fig1. definition image = rth(j-c) rth(c-a) established: 2004-03-18 revised : 2009-06-26
in case that the semiconductor packages are mounted on the pcb, the soldering should be performed under the following conditions. reflow soldering peak temperature : less than 260 temperature is measured at package surface point wave soldering (flow soldering) temp. of solder : 260 or less soak time : within 5 s number of flow : only 1 time manual soldering iron temperature : 350 or less (device lead temperature : 270 ? 10 s max.) soldering time : within 3 s number of manual soldering : only 1 time no. 11-184 product name : package : AN44067A-VF hsop034-p-0300a 8- number of reflow within 2 times 7b down rate 2 /s 5 /s 6tw high temp. region hold time within 60 s ( R 220 ) 5tp peak temp. hold time 10 s3 s 4tp peak temp. 255 +5 ? -0 3a rising rate 2 /s 5 /s 2 pre-heating temp. hold time 60 s 120 s 1t1 pre-heating temp. 150 180 recommended soldering conditions total pages page 21 industrial devices company, panasonic corporation 2012/3/7 prepared revised no mark contents value recommended soldering conditions max. 260 reflow peak temp. : 140 160 180 200 220 240 255 time t1 t1 tw tp tp 220 260 a b 260
because the taping and the magazine materials are not the heat-resistant materials, the bake at 125 cannot be done. therefore, please solder everything or control everything in the rule time. please keep them in an equal environment with the moisture-proof packaging or dry box. (temperature: room temperature, relative humidity: 30% or less. ) to control storage time, when bake in the taping and the magazine is necessary, it is necessary for each type to set a bake condition. please inquire of our company. storage environment conditions: keep the following conditions ta=5 30 ? rh=30 % 70 %. storage period before opening dry pack shall be 1year from a shipping day under ta=5 30 ? rh=30 % 70 %. when the storage exceeds, bake at 125 with 15 h to 25 h. baking cycle should be only one time. please be cautious of solderability at baking. in case that use reflow two times, 2nd reflow must be finished within 168 hours. remove flux sufficiently from product in the washing process. ( flux : chlorineless rosin flux is recommended.) in case that use ultrasonic for product washing, there is the possibility that the resonance may occur due to the frequency and shape of pcb. it may be affected to the strength of lead. please be cautious of this matter. no. AN44067A-VF limitation, low temperature bake condition 40 / 25 %rh or less / 192 h 11-184 2 storage environment after dry pack opening open dry pack storage environment kept up to soldering (at 30 /70 %rh max. , within 168h ) soldering bake at 125 with 15 h to 25 h *please refer to the following when doing at the low temperature bake. when the storage time exceeds 3 note recommended soldering conditions total pages page 22 industrial devices company, panasonic corporation 2012/3/7 prepared revised
industrial devices company, panasonic corporation 2012.03.13 prepared revised recommended land pattern total pages page 11
specifications of packing by the embossment tape ( specifications for dampproof packing of the reel without the inner carton) total pages 3 packing specification page 1 revised semiconductor company panasonic corporation prepared 2009.03.09 an12345a-nb 3000pcs. (3n)an12345a-nb 1000 (3n)2 10n112200-nb 108010 an12345a-nb an12345a-nb 1.23-45 410n112300 2058 usp4b42516 an12345a-nb 12345678 3000 23456789 3000 34567890 3000 45678901 3000 307 150000 panasonic m made in japan embossment carrier tape top cover tape an12345a-nb 90000pcs. (3n)an12345a-nb 1000 (3n)2 10n112200-nb 108010 an12345a-nb an12345a-nb 1.23-45 410n112300 2058 usp4b42516 an12345a-nb 12345678 3000 23456789 3000 34567890 3000 45678901 3000 307 150000 panasonic m made in japan corrugated cardboard for partition outer box laminated aluminum bag inner frame c3 label (sampl) reel desiccant c3 label (sampl)
3000 pcs reel 1pcs packing case 15000 pcs reel pcs v f form ic quantity contents packing quantity 2) reel 3) packing cas e package : hsop034-p-0300a unit : mm packing 1) tape reel total pages packing specification page 2 revised semiconductor company panasonic corporation prepared 1 2 draw out direction emboss carrier ta p e 25.5 330 360 360 220
semiconductor company panasonic corporation package : hsop034-p-0300a unit : mm prepared revised packing specification total pages page 3 dimensions & tolerance top-coverd-tape range 3
industrial devices company, panasonic corporation 1 kotari-yakemachi, nagaokakyo city, kyoto 617-8520, japan tel:075-951-8151
mouser electronics authorized distributor click to view pricing, inventory, delivery & lifecycle information: panasonic: ? AN44067A-VF

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